Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvmlsl_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)Vector arithmetic / Multiply / Multiply-accumulate and widen
Description
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

UMLSL Vd.4S,Vn.4H,Vm.4H

Argument Preparation
a register: Vd.4Sb register: Vn.4Hc register: Vm.4H
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1 * element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;