Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint8x16_tvmlsq_s8(int8x16_t a, int8x16_t b, int8x16_t c)Vector arithmetic / Multiply / Multiply-accumulate
Description
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
Results
Vd.16B result
This intrinsic compiles to the following instructions:

MLS Vd.16B,Vn.16B,Vm.16B

Argument Preparation
a register: Vd.16Bb register: Vn.16Bc register: Vm.16B
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1) * UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;