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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint16x8_tvmovn_high_s32(int16x4_t r, int32x4_t a)Move / Narrow
Description
Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

XTN2 Vd.8H,Vn.4S

Argument Preparation
r register: Vd.4Ha register: Vn.4S
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand = V[n];
bits(datasize) result;
bits(2*esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, 2*esize];
    Elem[result, e, esize] = element<esize-1:0>;
Vpart[d, part] = result;