Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvmull_high_lane_u16(uint16x8_t a, uint16x4_t v, const int lane)Scalar arithmetic / Vector multiply by scalar and widen
Description
Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation
a register: Vn.8Hv register: Vm.4Hlane minimum: 0; maximum: 3
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, 2*esize] = (element1 * element2)<2*esize-1:0>;

V[d] = result;