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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvmull_high_n_s16(int16x8_t a, int16_t b)Scalar arithmetic / Vector multiply by scalar and widen
Description
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SMULL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation
a register: Vn.8Hb register: Vm.H[0]
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, 2*esize] = (element1 * element2)<2*esize-1:0>;

V[d] = result;