Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat16x8_tvmulq_lane_f16(float16x8_t a, float16x4_t v, const int lane)Vector arithmetic / Multiply / Multiplication
Description
Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

FMUL Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation
a register: Vn.8Hv register: Vm.4Hlane minimum: 0; maximum: 3
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR[]);

V[d] = result;