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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat64x1_tvmulx_laneq_f64(float64x1_t a, float64x2_t v, const int lane)Vector arithmetic / Multiply / Multiply extended
Description
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
Results
Dd result
This intrinsic compiles to the following instructions:

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation
a register: Dnv register: Vm.2Dlane minimum: 0; maximum: 1
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];

bits(esize) element1;
bits(esize) element2;
FPCRType fpcr    = FPCR[];
boolean merge    = elements == 1 && IsMerging(fpcr);
bits(128) result = if merge then V[n] else Zeros();

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMulX(element1, element2, fpcr);
V[d] = result;