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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint16x4_tvmvn_s16(int16x4_t a)Logical / Bitwise NOT
Description
Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.8B result
This intrinsic compiles to the following instructions:

MVN Vd.8B,Vn.8B

Argument Preparation
a register: Vn.8B
Architectures
v7, A32, A64

Operation

The description of NOT gives the operational pseudocode for this instruction.