vmvnq_u8
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Neon | uint8x16_t | vmvnq_u8 | (uint8x16_t a) | Logical / Bitwise NOT | |
Description Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register. Results Vd.16B result This intrinsic compiles to the following instructions: MVN Argument Preparation a register: Vn.16B Architectures v7, A32, A64 OperationThe description of NOT gives the operational pseudocode for this instruction. | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.