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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat16x8_tvnegq_f16(float16x8_t a)Logical / Negate
Description
Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

FNEG Vd.8H,Vn.8H

Argument Preparation
a register: Vn.8H
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    if neg then
        element = FPNeg(element);
    else
        element = FPAbs(element);
    Elem[result, e, esize] = element;

V[d] = result;