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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint8x16_tvornq_u8(uint8x16_t a, uint8x16_t b)Logical / OR-NOT
Description
Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.
Results
Vd.16B result
This intrinsic compiles to the following instructions:

ORN Vd.16B,Vn.16B,Vm.16B

Argument Preparation
a register: Vn.16Bb register: Vm.16B
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

if invert then operand2 = NOT(operand2);

case op of
    when LogicalOp_AND
        result = operand1 AND operand2;
    when LogicalOp_ORR
        result = operand1 OR operand2;

V[d] = result;