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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64x1_tvorr_s64(int64x1_t a, int64x1_t b)Logical / OR
Description
Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.
Results
Vd.8B result
This intrinsic compiles to the following instructions:

ORR Vd.8B,Vn.8B,Vm.8B

Argument Preparation
a register: Vn.8Bb register: Vm.8B
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

if invert then operand2 = NOT(operand2);

case op of
    when LogicalOp_AND
        result = operand1 AND operand2;
    when LogicalOp_ORR
        result = operand1 OR operand2;

V[d] = result;