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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64x1_tvpadal_s32(int64x1_t a, int32x2_t b)Vector arithmetic / Pairwise arithmetic / Pairwise addition and widen
Description
Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
Results
Vd.1D result
This intrinsic compiles to the following instructions:

SADALP Vd.1D,Vn.2S

Argument Preparation
a register: Vd.1Db register: Vn.2S
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(2*esize) sum;
integer op1;
integer op2;

if acc then result = V[d];
for e = 0 to elements-1
    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
    sum = (op1 + op2)<2*esize-1:0>;
    if acc then
        Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
    else
        Elem[result, e, 2*esize] = sum;

V[d] = result;