vpaddlq_s8
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
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Neon | int16x8_t | vpaddlq_s8 | (int8x16_t a) | Vector arithmetic / Pairwise arithmetic / Pairwise addition and widen | |
Description Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. Results Vd.8H result This intrinsic compiles to the following instructions: SADDLP Argument Preparation a register: Vn.16B Architectures v7, A32, A64 Operation
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