Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvpaddq_u32(uint32x4_t a, uint32x4_t b)Vector arithmetic / Pairwise arithmetic / Pairwise addition
Description
Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

ADDP Vd.4S,Vn.4S,Vm.4S

Argument Preparation
a register: Vn.4Sb register: Vm.4S
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[concat, 2*e, esize];
    element2 = Elem[concat, (2*e)+1, esize];
    Elem[result, e, esize] = element1 + element2;

V[d] = result;