Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64_tvqaddd_s64(int64_t a, int64_t b)Vector arithmetic / Add / Saturating addition
Description
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Results
Dd result
This intrinsic compiles to the following instructions:

SQADD Dd,Dn,Dm

Argument Preparation
a register: Dnb register: Dm
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;