Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvqdmulhq_s32(int32x4_t a, int32x4_t b)Vector arithmetic / Multiply / Saturating multiply
Description
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SQDMULH Vd.4S,Vn.4S,Vm.4S

Argument Preparation
a register: Vn.4Sb register: Vm.4S
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if rounding then 1 << (esize - 1) else 0;
integer element1;
integer element2;
integer product;
boolean sat;

for e = 0 to elements-1
    element1 = SInt(Elem[operand1, e, esize]);
    element2 = SInt(Elem[operand2, e, esize]);
    product = (2 * element1 * element2) + round_const;
    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
    if sat then FPSR.QC = '1';

V[d] = result;