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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvqdmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)Vector arithmetic / Multiply / Saturating multiply by scalar and widen
Description
Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation
a register: Vn.8Hv register: Vm.8Hlane minimum: 0; maximum: 7
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
boolean sat;

for e = 0 to elements-1
    element1 = SInt(Elem[operand1, e, esize]);
    element2 = SInt(Elem[operand2, e, esize]);
    (product, sat) = SignedSatQ(2 * element1 * element2, 2*esize);
    Elem[result, e, 2*esize] = product;
    if sat then FPSR.QC = '1';

V[d] = result;