Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64x2_tvqdmull_s32(int32x2_t a, int32x2_t b)Vector arithmetic / Multiply / Saturating multiply
Description
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

SQDMULL Vd.2D,Vn.2S,Vm.2S

Argument Preparation
a register: Vn.2Sb register: Vm.2S
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
boolean sat;

for e = 0 to elements-1
    element1 = SInt(Elem[operand1, e, esize]);
    element2 = SInt(Elem[operand2, e, esize]);
    (product, sat) = SignedSatQ(2 * element1 * element2, 2*esize);
    Elem[result, e, 2*esize] = product;
    if sat then FPSR.QC = '1';

V[d] = result;