Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64x2_tvqnegq_s64(int64x2_t a)Logical / Saturating Negate
Description
Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

SQNEG Vd.2D,Vn.2D

Argument Preparation
a register: Vn.2D
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
integer element;
boolean sat;

for e = 0 to elements-1
    element = SInt(Elem[operand, e, esize]);
    if neg then
        element = -element;
    else
        element = Abs(element);
    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);         
    if sat then FPSR.QC = '1';

V[d] = result;