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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x2_tvqrdmlsh_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)Vector arithmetic / Multiply / Saturating multiply-accumulate by element
Description
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.
Results
Vd.2S result
This intrinsic compiles to the following instructions:

SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation
a register: Vd.2Sb register: Vn.2Sv register: Vm.4Slane minimum: 0; maximum: 3
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
integer rounding_const = if rounding then 1 << (esize - 1) else 0;
integer element1;
integer element2;
integer element3;
integer product;
boolean sat;

for e = 0 to elements-1
    element1 = SInt(Elem[operand1, e, esize]);
    element2 = SInt(Elem[operand2, e, esize]);
    element3 = SInt(Elem[operand3, e, esize]);
    if sub_op then
        accum = ((element3 << esize) - 2 * (element1 * element2) + rounding_const);
    else
        accum = ((element3 << esize) + 2 * (element1 * element2) + rounding_const);
    (Elem[result, e, esize], sat) = SignedSatQ(accum >> esize, esize);
    if sat then FPSR.QC = '1';

V[d] = result;