Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvqrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)Shift / Right / Vector saturating rounding shift right and narrow
Description
Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

UQRSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation
r register: Vd.2Sa register: Vn.2Dn minimum: 1; maximum: 32
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n];
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;
boolean sat;

for e = 0 to elements-1
    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
    if sat then FPSR.QC = '1';

Vpart[d, part] = result;