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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32_tvqrshrnd_n_s64(int64_t a, const int n)Shift / Right / Vector saturating rounding shift right and narrow
Description
Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.
Results
Sd result
This intrinsic compiles to the following instructions:

SQRSHRN Sd,Dn,#n

Argument Preparation
a register: Dnn minimum: 1; maximum: 32
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n];
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;
boolean sat;

for e = 0 to elements-1
    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
    if sat then FPSR.QC = '1';

Vpart[d, part] = result;