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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvqshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)Shift / Right / Vector saturating shift right and narrow
Description
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SQSHRUN2 Vd.4S,Vn.2D,#n

Argument Preparation
r register: Vd.2Sa register: Vn.2Dn minimum: 1; maximum: 32
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n];
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;
boolean sat;

for e = 0 to elements-1
    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
    if sat then FPSR.QC = '1';

Vpart[d, part] = result;