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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint8x8_tvrbit_u8(uint8x8_t a)Vector manipulation / Reverse bits within elements
Description
Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.8B result
This intrinsic compiles to the following instructions:

RBIT Vd.8B,Vn.8B

Argument Preparation
a register: Vn.8B
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
bits(esize) element;
bits(esize) rev;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    for i = 0 to esize-1
        rev<esize-1-i> = element<i>;
    Elem[result, e, esize] = rev;

V[d] = result;