vreinterpret_f16_u64
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Neon | float16x4_t | vreinterpret_f16_u64 | (uint64x1_t a) | Data type conversion / Reinterpret casts | |
Description Vector reinterpret cast operation Results Vd.4H result This intrinsic compiles to the following instructions: Argument Preparation a register: Vd.1D Architectures v7, A32, A64 OperationNo operation information. | |||||
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