vreinterpret_p64_f16
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Neon | poly64x1_t | vreinterpret_p64_f16 | (float16x4_t a) | Data type conversion / Reinterpret casts | |
Description Vector reinterpret cast operation Results Vd.1D result This intrinsic compiles to the following instructions: Argument Preparation a register: Vd.4H Architectures A32, A64 OperationNo operation information. | |||||
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