SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64x1_tvreinterpret_u64_s16(int16x4_t a)Data type conversion / Reinterpret casts
Description
Vector reinterpret cast operation
Results
Vd.1D result
This intrinsic compiles to the following instructions:
Argument Preparation
a register: Vd.4H
Architectures
v7, A32, A64

Operation

No operation information.