vreinterpretq_f16_p128
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Neon | float16x8_t | vreinterpretq_f16_p128 | (poly128_t a) | Data type conversion / Reinterpret casts | |
Description Vector reinterpret cast operation Results Vd.8H result This intrinsic compiles to the following instructions: Argument Preparation a register: Vd.1Q Architectures A32, A64 OperationNo operation information. | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.