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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvrev64q_s32(int32x4_t vec)Vector manipulation / Reverse elements
Description
Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

REV64 Vd.4S,Vn.4S

Argument Preparation
vec register: Vn.4S
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
integer element = 0;
integer rev_element;
for c = 0 to containers-1
    rev_element = element + elements_per_container - 1;
    for e = 0 to elements_per_container-1
        Elem[result, rev_element, esize] = Elem[operand, element, esize];
        element = element + 1;
        rev_element = rev_element - 1;

V[d] = result;