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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat64x2_tvrnd64xq_f64(float64x2_t a)Vector arithmetic / Rounding
Description
Floating-point Round to 64-bit Integer, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values that fit into a 64-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.
Results
Vd result
This intrinsic compiles to the following instructions:

FRINT64X Vd.2D,Vn.2D

Argument Preparation
a register: Vn
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPRoundIntN(element, FPCR[], rounding, intsize);

V[d] = result;