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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64_tvrshrd_n_u64(uint64_t a, const int n)Shift / Right / Vector rounding shift right
Description
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
Results
Dd result
This intrinsic compiles to the following instructions:

URSHR Dd,Dn,#n

Argument Preparation
a register: Dnn minimum: 1; maximum: 64
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand  = V[n];
bits(datasize) operand2;
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;

operand2 = if accumulate then V[d] else Zeros();
for e = 0 to elements-1
    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

V[d] = result;