Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvrshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)Shift / Right / Vector rounding shift right and narrow
Description
Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

RSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation
r register: Vd.2Sa register: Vn.2Dn minimum: 1; maximum: 32
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n];
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;

for e = 0 to elements-1
    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
    Elem[result, e, esize] = element<esize-1:0>;

Vpart[d, part] = result;