vrsra_n_s16
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
---|---|---|---|---|---|
Neon | int16x4_t | vrsra_n_s16 | (int16x4_t a, int16x4_t b, const int n) | Shift / Right / Vector rounding shift right and accumulate | |
Description Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA. Results Vd.4H result This intrinsic compiles to the following instructions: SRSRA Argument Preparation a register: Vd.4Hb register: Vn.4Hn minimum: 1; maximum: 16 Architectures v7, A32, A64 Operation
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