vrsra_n_u32
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
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Neon | uint32x2_t | vrsra_n_u32 | (uint32x2_t a, uint32x2_t b, const int n) | Shift / Right / Vector rounding shift right and accumulate | |
Description Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA. Results Vd.2S result This intrinsic compiles to the following instructions: URSRA Argument Preparation a register: Vd.2Sb register: Vn.2Sn minimum: 1; maximum: 32 Architectures v7, A32, A64 Operation
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