vrsubhn_s32
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
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Neon | int16x4_t | vrsubhn_s32 | (int32x4_t a, int32x4_t b) | Vector arithmetic / Subtract / Narrowing subtraction | |
Description Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. Results Vd.4H result This intrinsic compiles to the following instructions: RSUBHN Argument Preparation a register: Vn.4Sb register: Vm.4S Architectures v7, A32, A64 Operation
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