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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)Cryptography / SHA1
Description
SHA1 hash update (majority).
Results
Qd result
This intrinsic compiles to the following instructions:

SHA1M Qd,Sn,Vm.4S

Argument Preparation
hash_abcd register: Qdhash_e register: Snwk register: Vm.4S
Architectures
A32, A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) X = V[d];
bits(32)  Y = V[n];     // Note: 32 not 128 bits wide
bits(128) W = V[m];
bits(32)  t;

for e = 0 to 3
    t = SHAmajority(X<63:32>, X<95:64>, X<127:96>);
    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
    X<63:32> = ROL(X<63:32>, 30);
    <Y, X> = ROL(Y : X, 32);
V[d] = X;