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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)Cryptography / SHA1
Description
SHA1 schedule update 0.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SHA1SU0 Vd.4S,Vn.4S,Vm.4S

Argument Preparation
w0_3 register: Vd.4Sw4_7 register: Vn.4Sw8_11 register: Vm.4S
Architectures
A32, A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand1 = V[d];
bits(128) operand2 = V[n];
bits(128) operand3 = V[m];
bits(128) result;

result = operand2<63:0> : operand1<127:64>;
result = result EOR operand1 EOR operand3;
V[d] = result;