Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsha1su1q_u32(uint32x4_t tw0_3, uint32x4_t w12_15)Cryptography / SHA1
Description
SHA1 schedule update 1.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SHA1SU1 Vd.4S,Vn.4S

Argument Preparation
tw0_3 register: Vd.4Sw12_15 register: Vn.4S
Architectures
A32, A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand1 = V[d];
bits(128) operand2 = V[n];
bits(128) result;
bits(128) T = operand1 EOR LSR(operand2, 32);
result<31:0>   = ROL(T<31:0>,   1);
result<63:32>  = ROL(T<63:32>,  1);
result<95:64>  = ROL(T<95:64>,  1);
result<127:96> = ROL(T<127:96>, 1) EOR ROL(T<31:0>, 2);
V[d] = result;