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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)Cryptography / SHA256
Description
SHA256 hash update (part 2).
Results
Qd result
This intrinsic compiles to the following instructions:

SHA256H2 Qd,Qn,Vm.4S

Argument Preparation
hash_efgh register: Qdhash_abcd register: Qnwk register: Vm.4S
Architectures
A32, A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) result;
if part1 then
    result = SHA256hash(V[d], V[n], V[m], TRUE);
else
    result = SHA256hash(V[n], V[d], V[m], FALSE);
V[d] = result;