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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7)Cryptography / SHA256
Description
SHA256 schedule update 0.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SHA256SU0 Vd.4S,Vn.4S

Argument Preparation
w0_3 register: Vd.4Sw4_7 register: Vn.4S
Architectures
A32, A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand1 = V[d];
bits(128) operand2 = V[n];
bits(128) result;
bits(128) T = operand2<31:0> : operand1<127:32>;
bits(32) elt;

for e = 0 to 3
    elt = Elem[T, e, 32];
    elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3);
    Elem[result, e, 32] = elt + Elem[operand1, e, 32];
V[d] = result;