Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64x2_tvsha512h2q_u64(uint64x2_t sum_ab, uint64x2_t hash_c_, uint64x2_t hash_ab)Cryptography / SHA512
Description
SHA512 Hash update part 2 takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma0 and majority functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register.
Results
Qd result
This intrinsic compiles to the following instructions:

SHA512H2 Qd,Qn,Vm.2D

Argument Preparation
sum_ab register: Qdhash_c_ register: Qnhash_ab
Architectures
A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vtmp;  
bits(64) NSigma0;
bits(64) tmp;
bits(128) X = V[n];
bits(128) Y = V[m];
bits(128) W = V[d];

NSigma0 =  ROR(Y<63:0>, 28) EOR ROR(Y<63:0>,34) EOR ROR(Y<63:0>,39);
Vtmp<127:64> = (X<63:0> AND Y<127:64>) EOR (X<63:0> AND Y<63:0>) EOR (Y<127:64> AND Y<63:0>);
Vtmp<127:64> = (Vtmp<127:64> + NSigma0 +  W<127:64>);
NSigma0 =  ROR(Vtmp<127:64>, 28) EOR ROR(Vtmp<127:64>,34) EOR ROR(Vtmp<127:64>,39);
Vtmp<63:0> =   (Vtmp<127:64> AND Y<63:0>) EOR (Vtmp<127:64> AND Y<127:64>) EOR (Y<127:64> AND Y<63:0>);
Vtmp<63:0> =   (Vtmp<63:0> + NSigma0 + W<63:0>);

V[d] = Vtmp;