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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64x2_tvsha512su0q_u64(uint64x2_t w0_1, uint64x2_t w2_)Cryptography / SHA512
Description
SHA512 Schedule Update 0 takes the values from the two 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the gamma0 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

SHA512SU0 Vd.2D,Vn.2D

Argument Preparation
w0_1 register: Vd.2Dw2_ register: Vn.2D
Architectures
A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(64) sig0;
bits(128) Vtmp;
bits(128) X = V[n];
bits(128) W = V[d]; 
sig0 = ROR(W<127:64>, 1) EOR ROR(W<127:64>, 8) EOR ('0000000':W<127:71>);
Vtmp<63:0> = W<63:0> + sig0;
sig0 = ROR(X<63:0>, 1) EOR ROR(X<63:0>, 8) EOR ('0000000':X<63:7>);
Vtmp<127:64> = W<127:64> + sig0;
V[d] = Vtmp;