Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvshll_n_s16(int16x4_t a, const int n)Shift / Left / Vector shift left and widen
Description
Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SSHLL Vd.4S,Vn.4H,#n

Argument Preparation
a register: Vn.4Hn minimum: 0; maximum: 15
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = Vpart[n, part];
bits(datasize*2) result;
integer element;

for e = 0 to elements-1
    element = Int(Elem[operand, e, esize], unsigned) << shift;
    Elem[result, e, 2*esize] = element<2*esize-1:0>;

V[d] = result;