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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvshll_n_u16(uint16x4_t a, const int n)Shift / Left / Vector shift left and widen
Description
Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

USHLL Vd.4S,Vn.4H,#n

Argument Preparation
a register: Vn.4Hn minimum: 0; maximum: 15
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = Vpart[n, part];
bits(datasize*2) result;
integer element;

for e = 0 to elements-1
    element = Int(Elem[operand, e, esize], unsigned) << shift;
    Elem[result, e, 2*esize] = element<2*esize-1:0>;

V[d] = result;