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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)Shift / Right / Vector shift right and narrow
Description
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SHRN2 Vd.4S,Vn.2D,#n

Argument Preparation
r register: Vd.2Sa register: Vn.2Dn minimum: 1; maximum: 32
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n];
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;

for e = 0 to elements-1
    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
    Elem[result, e, esize] = element<esize-1:0>;

Vpart[d, part] = result;