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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsm3partw1q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)Cryptography / SM3
Description
SM3PARTW1 takes three 128-bit vectors from the three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SM3PARTW1 Vd.4S,Vn.4S,Vm.4S

Argument Preparation
a register: Vd.4Sb c
Architectures
A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m];
bits(128) Vn = V[n];
bits(128) Vd = V[d];
bits(128) result; 

result<95:0> = (Vd EOR Vn)<95:0> EOR (ROL(Vm<127:96>,15):ROL(Vm<95:64>,15):ROL(Vm<63:32>,15));

for i = 0 to 3
    if i == 3 then 
        result<127:96> = (Vd EOR Vn)<127:96> EOR (ROL(result<31:0>,15));
    result<(32*i)+31:(32*i)> = result<(32*i)+31:(32*i)> EOR ROL(result<(32*i)+31:(32*i)>,15) EOR ROL(result<(32*i)+31:(32*i)>,23);
V[d] = result;