SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsm3ss1q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)Cryptography / SM3
Description
SM3SS1 rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SM3SS1 Vd.4S,Vn.4S,Vm.4S,Va.4S

Argument Preparation
a register: Vn.4Sb c
Architectures
A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m];
bits(128) Vn = V[n];
bits(128) Vd = V[d];
bits(128) Va = V[a];
Vd<127:96> = ROL((ROL(Vn<127:96>,12) + Vm<127:96> + Va<127:96>) , 7);
Vd<95:0> = Zeros();
V[d] = Vd;