vsm3ss1q_u32
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
---|---|---|---|---|---|
Neon | uint32x4_t | vsm3ss1q_u32 | (uint32x4_t a, uint32x4_t b, uint32x4_t c) | Cryptography / SM3 | |
Description SM3SS1 rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0. Results Vd.4S result This intrinsic compiles to the following instructions: SM3SS1 Argument Preparation a register: Vn.4Sb c Architectures A64 Operation |