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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvsm3tt1bq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)Cryptography / SM3
Description
SM3TT1B takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values:
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SM3TT1B Vd.4S,Vn.4S,Vm.4S[imm2]

Argument Preparation
a register: Vd.4Sb c imm2 minimum: 0; maximum: 3
Architectures
A64

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m];
bits(128) Vn = V[n];
bits(128) Vd = V[d];
bits(32) WjPrime;
bits(128) result; 
bits(32) TT1;
bits(32) SS2;

WjPrime = Elem[Vm,i,32];
SS2 = Vn<127:96> EOR ROL(Vd<127:96>,12); 
TT1 = (Vd<127:96> AND Vd<63:32>) OR (Vd<127:96> AND Vd<95:64>) OR (Vd<63:32> AND Vd<95:64>); 
TT1 = (TT1 + Vd<31:0> + SS2 + WjPrime)<31:0>;
result<31:0> = Vd<63:32>;
result<63:32> = ROL(Vd<95:64>,9); 
result<95:64> = Vd<127:96>; 
result<127:96> = TT1; 
V[d] = result;