Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64x1_tvsqadd_u64(uint64x1_t a, int64x1_t b)Vector arithmetic / Add / Saturating addition
Description
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
Results
Dd result
This intrinsic compiles to the following instructions:

USQADD Dd,Dn

Argument Preparation
a register: Ddb register: Dn
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;